diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 1b5059adb8..6a5ce53a40 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -72,10 +72,6 @@ static void haswell_setup_misc(void)
 	reg32 |= (1 << 9) | (1 << 10);
 	mchbar_write32(SAPMCTL, reg32);
 
-	/* Enable SA Clock Gating */
-	reg32 = mchbar_read32(SAPMCTL);
-	mchbar_write32(SAPMCTL, reg32 | 1);
-
 	reg32 = mchbar_read32(INTRDIRCTL);
 	reg32 |= (1 << 4) | (1 << 5);
 	mchbar_write32(INTRDIRCTL, reg32);
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index e819838175..84d9fb5792 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -464,6 +464,9 @@ static void northbridge_init(struct device *dev)
 
 	disable_devices();
 
+	/* Enable SA Clock Gating */
+	mchbar_setbits32(SAPMCTL, 1 << 0);
+
 	/*
 	 * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU
 	 * that BIOS has initialized memory and power management.