From 5bb8b30c0385b119686d7255fd28c480af5e5837 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 9 Mar 2026 22:39:51 +0100 Subject: [PATCH] nb/intel/haswell: Enable SA clock gating later Reference code version 1.9.1 sets `SAPMCTL` bit 0 just before setting `BIOS_RESET_CPL` bits 0 and 1. Do the same thing in coreboot. Change-Id: I36e24d2a3bd754e56df59a1e996d285ec6bf5205 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/91632 Reviewed-by: Patrick Rudolph Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) Reviewed-by: Alicja Michalska --- src/northbridge/intel/haswell/early_init.c | 4 ---- src/northbridge/intel/haswell/northbridge.c | 3 +++ 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 1b5059adb8..6a5ce53a40 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -72,10 +72,6 @@ static void haswell_setup_misc(void) reg32 |= (1 << 9) | (1 << 10); mchbar_write32(SAPMCTL, reg32); - /* Enable SA Clock Gating */ - reg32 = mchbar_read32(SAPMCTL); - mchbar_write32(SAPMCTL, reg32 | 1); - reg32 = mchbar_read32(INTRDIRCTL); reg32 |= (1 << 4) | (1 << 5); mchbar_write32(INTRDIRCTL, reg32); diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index e819838175..84d9fb5792 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -464,6 +464,9 @@ static void northbridge_init(struct device *dev) disable_devices(); + /* Enable SA Clock Gating */ + mchbar_setbits32(SAPMCTL, 1 << 0); + /* * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU * that BIOS has initialized memory and power management.