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soc/intel/pantherlake: Add new PCI and CPU IDs

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This commit adds the relevant IDs to support new Panther Lake (PTL)
System on Chips (SoCs). The CPU profiles are aligned with the matching
definition from Panther Lake Firmware Support Package (FSP) revision
3144.01.

TEST=A Fatcat device with CPUID 0xc06c1 and MCH_ID 0xb003 booted with
     the relevant information printed in corebot logs.
     [DEBUG]  CPU: ID c06c1, Pantherlake B0, ucode: 00000105
     [DEBUG]  MCH: device id b003 (rev 06) is Pantherlake U
     [DEBUG]  PCH: device id e401 (rev 01) is Pantherlake SOC-H SuperSKU
     [DEBUG]  IGD: device id b090 (rev 00) is Pantherlake-U GT2

Change-Id: I66efe51a94edfffc2546817d06a63a9c4b51aa81
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88130
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This commit is contained in:
Jamie Ryu 2025-06-17 13:08:32 -07:00 • committed by Jérémy Compostella
commit 57bffed893
7 changed files with 29 additions and 0 deletions
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2
src/include/cpu/intel/cpu_ids.h
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@ -87,6 +87,8 @@
#define CPUID_LUNARLAKE_A0_2 0xb06d1
#define CPUID_ARROWLAKE_H_A0 0xc0652
#define CPUID_PANTHERLAKE_A0 0xc06c0
#define CPUID_PANTHERLAKE_B0_1 0xc06c1
#define CPUID_PANTHERLAKE_B0_2 0xc06c2
#define CPUID_SNOWRIDGE_A0 0x80660
#define CPUID_SNOWRIDGE_A1 0x80661
#define CPUID_SNOWRIDGE_A2 0x80662