From 57bffed89357b6af563e8514e25e8605a99c5b85 Mon Sep 17 00:00:00 2001 From: Jamie Ryu Date: Tue, 17 Jun 2025 13:08:32 -0700 Subject: [PATCH] soc/intel/pantherlake: Add new PCI and CPU IDs This commit adds the relevant IDs to support new Panther Lake (PTL) System on Chips (SoCs). The CPU profiles are aligned with the matching definition from Panther Lake Firmware Support Package (FSP) revision 3144.01. TEST=A Fatcat device with CPUID 0xc06c1 and MCH_ID 0xb003 booted with the relevant information printed in corebot logs. [DEBUG] CPU: ID c06c1, Pantherlake B0, ucode: 00000105 [DEBUG] MCH: device id b003 (rev 06) is Pantherlake U [DEBUG] PCH: device id e401 (rev 01) is Pantherlake SOC-H SuperSKU [DEBUG] IGD: device id b090 (rev 00) is Pantherlake-U GT2 Change-Id: I66efe51a94edfffc2546817d06a63a9c4b51aa81 Signed-off-by: Jeremy Compostella Signed-off-by: Jamie Ryu Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/88130 Reviewed-by: Paul Menzel Reviewed-by: Bora Guvendik Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Cliff Huang --- src/include/cpu/intel/cpu_ids.h | 2 ++ src/include/device/pci_ids.h | 6 ++++++ src/soc/intel/common/block/cpu/mp_init.c | 2 ++ src/soc/intel/common/block/graphics/graphics.c | 1 + src/soc/intel/common/block/systemagent/systemagent.c | 5 +++++ src/soc/intel/pantherlake/bootblock/report_platform.c | 8 ++++++++ src/soc/intel/pantherlake/chip.h | 5 +++++ 7 files changed, 29 insertions(+) diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 59900077d9..70e5b7b0c3 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -87,6 +87,8 @@ #define CPUID_LUNARLAKE_A0_2 0xb06d1 #define CPUID_ARROWLAKE_H_A0 0xc0652 #define CPUID_PANTHERLAKE_A0 0xc06c0 +#define CPUID_PANTHERLAKE_B0_1 0xc06c1 +#define CPUID_PANTHERLAKE_B0_2 0xc06c2 #define CPUID_SNOWRIDGE_A0 0x80660 #define CPUID_SNOWRIDGE_A1 0x80661 #define CPUID_SNOWRIDGE_A2 0x80662 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 85de6a5cfb..93d2e81e61 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4401,6 +4401,7 @@ #define PCI_DID_INTEL_PTL_H_GT2_1 0xb080 #define PCI_DID_INTEL_PTL_H_GT2_2 0xb0a0 #define PCI_DID_INTEL_PTL_H_GT2_3 0xb0b0 +#define PCI_DID_INTEL_PTL_H_GT2_4 0xb08f #define PCI_DID_INTEL_WCL_GT2_1 0xfd80 #define PCI_DID_INTEL_WCL_GT2_2 0xfd81 @@ -4557,10 +4558,15 @@ #define PCI_DID_INTEL_LNL_M_ID_1 0x6410 #define PCI_DID_INTEL_PTL_U_ID_1 0xb000 #define PCI_DID_INTEL_PTL_U_ID_2 0xb003 +#define PCI_DID_INTEL_PTL_U_ID_3 0xb01a #define PCI_DID_INTEL_PTL_H_ID_1 0xb001 #define PCI_DID_INTEL_PTL_H_ID_2 0xb002 #define PCI_DID_INTEL_PTL_H_ID_3 0xb004 #define PCI_DID_INTEL_PTL_H_ID_4 0xb00a +#define PCI_DID_INTEL_PTL_H_ID_5 0xb00b +#define PCI_DID_INTEL_PTL_H_ID_6 0xb00c +#define PCI_DID_INTEL_PTL_H_ID_7 0xb005 +#define PCI_DID_INTEL_PTL_H_ID_8 0xb009 #define PCI_DID_INTEL_SNR_ID 0x09a2 #define PCI_DID_INTEL_WCL_ID_1 0xfd00 #define PCI_DID_INTEL_WCL_ID_2 0xfd01 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 16b77b0352..638aa07f29 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -34,6 +34,8 @@ static struct device_operations cpu_dev_ops = { static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_WILDCATLAKE_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_PANTHERLAKE_A0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_PANTHERLAKE_B0_1, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_PANTHERLAKE_B0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 165727ef0e..9666c49f96 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -348,6 +348,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_H_GT2_1, PCI_DID_INTEL_PTL_H_GT2_2, PCI_DID_INTEL_PTL_H_GT2_3, + PCI_DID_INTEL_PTL_H_GT2_4, PCI_DID_INTEL_LNL_M_GT2, PCI_DID_INTEL_RPL_U_GT1, PCI_DID_INTEL_RPL_U_GT2, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 8b623fc9e7..f98606a18d 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -429,10 +429,15 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_WCL_ID_2, PCI_DID_INTEL_PTL_U_ID_1, PCI_DID_INTEL_PTL_U_ID_2, + PCI_DID_INTEL_PTL_U_ID_3, PCI_DID_INTEL_PTL_H_ID_1, PCI_DID_INTEL_PTL_H_ID_2, PCI_DID_INTEL_PTL_H_ID_3, PCI_DID_INTEL_PTL_H_ID_4, + PCI_DID_INTEL_PTL_H_ID_5, + PCI_DID_INTEL_PTL_H_ID_6, + PCI_DID_INTEL_PTL_H_ID_7, + PCI_DID_INTEL_PTL_H_ID_8, PCI_DID_INTEL_LNL_M_ID, PCI_DID_INTEL_LNL_M_ID_1, PCI_DID_INTEL_MTL_M_ID, diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c index 0cca50669b..099075417e 100644 --- a/src/soc/intel/pantherlake/bootblock/report_platform.c +++ b/src/soc/intel/pantherlake/bootblock/report_platform.c @@ -21,6 +21,8 @@ static struct { const char *name; } cpu_table[] = { { CPUID_PANTHERLAKE_A0, "Pantherlake A0" }, + { CPUID_PANTHERLAKE_B0_1, "Pantherlake B0" }, + { CPUID_PANTHERLAKE_B0_2, "Pantherlake B0" }, }; static struct { @@ -29,10 +31,15 @@ static struct { } mch_table[] = { { PCI_DID_INTEL_PTL_U_ID_1, "Pantherlake U" }, { PCI_DID_INTEL_PTL_U_ID_2, "Pantherlake U" }, + { PCI_DID_INTEL_PTL_U_ID_3, "Pantherlake U" }, { PCI_DID_INTEL_PTL_H_ID_1, "Pantherlake H" }, { PCI_DID_INTEL_PTL_H_ID_2, "Pantherlake H" }, { PCI_DID_INTEL_PTL_H_ID_3, "Pantherlake H" }, { PCI_DID_INTEL_PTL_H_ID_4, "Pantherlake H" }, + { PCI_DID_INTEL_PTL_H_ID_5, "Pantherlake H" }, + { PCI_DID_INTEL_PTL_H_ID_6, "Pantherlake H" }, + { PCI_DID_INTEL_PTL_H_ID_7, "Pantherlake H" }, + { PCI_DID_INTEL_PTL_H_ID_8, "Pantherlake H" }, { PCI_DID_INTEL_WCL_ID_1, "Wildcatlake" }, { PCI_DID_INTEL_WCL_ID_2, "Wildcatlake" }, }; @@ -147,6 +154,7 @@ static struct { { PCI_DID_INTEL_PTL_H_GT2_1, "Pantherlake-H GT2" }, { PCI_DID_INTEL_PTL_H_GT2_2, "Pantherlake-H GT2" }, { PCI_DID_INTEL_PTL_H_GT2_3, "Pantherlake-H GT2" }, + { PCI_DID_INTEL_PTL_H_GT2_4, "Pantherlake-H GT2" }, { PCI_DID_INTEL_WCL_GT2_1, "Wildcatlake GT2" }, { PCI_DID_INTEL_WCL_GT2_2, "Wildcatlake GT2" }, }; diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 94c91a8e1c..92f561d6bf 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -86,10 +86,15 @@ static const struct soc_intel_pantherlake_power_map { } cpuid_to_ptl[] = { { PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W, PTL_H404_SKU }, { PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_15W, PTL_H204_SKU }, + { PCI_DID_INTEL_PTL_U_ID_3, PTL_U_2_CORE, TDP_15W, PTL_H404_SKU }, { PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W, PTL_H12XE_SKU }, { PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W, PTL_H484_SKU }, { PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU }, { PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU }, + { PCI_DID_INTEL_PTL_H_ID_5, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU }, + { PCI_DID_INTEL_PTL_H_ID_6, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU }, + { PCI_DID_INTEL_PTL_H_ID_7, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU }, + { PCI_DID_INTEL_PTL_H_ID_8, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU }, }; /* Types of display ports */