From 56922d914ba7687fb41434b7806b4b56affb5f2d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 21 Jan 2026 15:19:32 +0100 Subject: [PATCH] soc/amd/common/block/lpc: Report ESPI1 MMIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ESPI1 MMIO is reported in ACPI already, but the resource allocator must also know about it to avoid the allocation of resources in that range. TEST=Boot Gigabyte MZ33-AR1 and verify that ESPI1 address (0xfec30000) is reported for PCI device 00:00.14.3 in coreboot logs: dev: PCI: 00:00:14.3, index: 0x3, base: 0xfec30000, size: 0x1000 Change-Id: Ic4024e6aa37bd7568dcecbd7cae29be9ae587a7f Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/90853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel --- src/soc/amd/common/block/include/amdblocks/espi.h | 1 + src/soc/amd/common/block/lpc/lpc.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index b7ab06ee55..5781dea3af 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -7,6 +7,7 @@ /* eSPI MMIO base lives at an offset of 0x10000 from the address in SPI BAR. */ #define ESPI_OFFSET_FROM_BAR 0x10000 +#define ESPI1_OFFSET_FROM_BAR 0x20000 #define ESPI_DECODE 0x40 /* more bits defined in soc/common/amd/blocks/lpc/espi_def.h */ diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 2392d5f3e8..1aa81f66ca 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -123,6 +123,10 @@ static void lpc_read_resources(struct device *dev) /* Add a memory resource for the eSPI MMIO */ mmio_range(dev, idx++, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB); + /* Add a memory resource for the eSPI1 MMIO */ + if (CONFIG(SOC_AMD_COMMON_BLOCK_HAS_ESPI1)) + mmio_range(dev, idx++, SPI_BASE_ADDRESS + ESPI1_OFFSET_FROM_BAR, 4 * KiB); + /* FCH IOAPIC */ mmio_range(dev, idx++, IO_APIC_ADDR, 4 * KiB);