diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h
index b7ab06ee55..5781dea3af 100644
--- a/src/soc/amd/common/block/include/amdblocks/espi.h
+++ b/src/soc/amd/common/block/include/amdblocks/espi.h
@@ -7,6 +7,7 @@
 
 /* eSPI MMIO base lives at an offset of 0x10000 from the address in SPI BAR. */
 #define ESPI_OFFSET_FROM_BAR			0x10000
+#define ESPI1_OFFSET_FROM_BAR			0x20000
 
 #define ESPI_DECODE				0x40
 /* more bits defined in soc/common/amd/blocks/lpc/espi_def.h */
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 2392d5f3e8..1aa81f66ca 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -123,6 +123,10 @@ static void lpc_read_resources(struct device *dev)
 	/* Add a memory resource for the eSPI MMIO */
 	mmio_range(dev, idx++, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB);
 
+	/* Add a memory resource for the eSPI1 MMIO */
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_HAS_ESPI1))
+		mmio_range(dev, idx++, SPI_BASE_ADDRESS + ESPI1_OFFSET_FROM_BAR, 4 * KiB);
+
 	/* FCH IOAPIC */
 	mmio_range(dev, idx++, IO_APIC_ADDR, 4 * KiB);