diff --git a/src/vendorcode/amd/opensil/phoenix_poc/acpi.c b/src/vendorcode/amd/opensil/phoenix_poc/acpi.c
index fcdf167c12..75249b064d 100644
--- a/src/vendorcode/amd/opensil/phoenix_poc/acpi.c
+++ b/src/vendorcode/amd/opensil/phoenix_poc/acpi.c
@@ -4,7 +4,7 @@
 #include <Sil-api.h>
 #include <SilCommon.h>
 #include <xSIM-api.h>
-#include <FCH/Common/FchCommonCfg.h>
+#include <FCH/Common/FchCommon.h>
 
 #include "../opensil.h"
 
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/memmap.c b/src/vendorcode/amd/opensil/phoenix_poc/memmap.c
index eed1be7e5f..a9e8d1d2b7 100644
--- a/src/vendorcode/amd/opensil/phoenix_poc/memmap.c
+++ b/src/vendorcode/amd/opensil/phoenix_poc/memmap.c
@@ -2,7 +2,7 @@
 
 #include <SilCommon.h>
 #include <Sil-api.h> // needed above ApobCmn.h
-#include <ApobCmn.h>
+#include <APOB/Common/ApobCmn.h>
 #include <xPRF-api.h>
 
 #include "../opensil.h"
@@ -32,7 +32,6 @@ const char *opensil_get_hole_info_type(uint32_t type)
 		{ReservedCxl, "ReservedCxl"},
 		{ReservedCxlAlignment, "ReservedCxlAlignment"},
 		{ReservedCpuTmr, "ReservedCpuTmr"},
-		{ReservedRasEinj, "ReservedRasEinj"},
 		{MaxMemoryHoleTypes, "MaxMemoryHoleTypes"},
 	};
 
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c
index 587ab81e02..cdfe29fddd 100644
--- a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c
+++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c
@@ -4,8 +4,8 @@
 #include <device/pci_def.h>
 #include <Mpio/Common/MpioStructs.h>
 #include <Mpio/MpioClass-api.h>
-#include <NBIO/NbioClass-api.h>
-#include <RcMgr/DfX/RcManager4-api.h>
+#include <Nbio/NbioClass-api.h>
+#include <RcMgr/DfX/RcManager-api.h>
 #include <vendorcode/amd/opensil/opensil.h>
 #include <xSIM-api.h>
 
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template b/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template
index 2ddd3b4ec1..a93eaeed6a 100644
--- a/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template
+++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template
@@ -1,5 +1,3 @@
 CONFIG_PLAT_APOB_ADDRESS=##APOB_BASE##
 CONFIG_PSP_BIOS_BIN_BASE=##BIOS_ENTRY_BASE##
 CONFIG_PSP_BIOS_BIN_SIZE=##BIOS_ENTRY_SIZE##
-CONFIG_PLAT_NUMBER_SOCKETS=1
-CONFIG_SOC_F19M10=y
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c
index 5a037fecb5..243236a9ab 100644
--- a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c
+++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c
@@ -1,14 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <FCH/Common/FchCommonCfg.h>
-#include <FCH/Common/FchCore/FchSata/FchSata.h>
-#include <RcMgr/DfX/RcManager4-api.h>
+#include <FCH/Common/FchCommon.h>
+#include <RcMgr/DfX/RcManager-api.h>
 #include <amdblocks/reset.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <cpu/cpu.h>
 #include <device/device.h>
-#include <soc/soc_chip.h>
+#include <soc/amd/phoenix/chip.h>
 #include <static.h>
 #include <stdio.h>
 #include <xSIM-api.h>