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UPSTREAM: VIA C7 NANO: Fix early MTRR setting

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It would not be possible to set MTRR for range 1MiB to 4MiB.
Our RAMTOP is power of 2 and enabling cache for bottom
1MiB should cause no problems.

Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15238
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit d71cfd2041)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354191
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-06-16 21:14:25 +03:00 • committed by chrome-bot
commit 4eeefb31ed
1 changed files with 3 additions and 3 deletions
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6
src/cpu/via/car/cache_as_ram.inc
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@ -225,15 +225,15 @@ testok:
movl $(MTRR_DEF_TYPE_EN), %eax
wrmsr
/* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */
/* Enable caching for 0..CONFIG_RAMTOP. */
movl $MTRR_PHYS_BASE(0), %ecx
xorl %edx, %edx
movl $(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax
movl $(0x0 | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $MTRR_PHYS_MASK(0), %ecx
movl $0x0000000f, %edx /* AMD 40 bit 0xff */
movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
/* Cache XIP_ROM area to speedup coreboot code. */