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UPSTREAM: intel/broadwell: Remove old USBDEBUG backup store in CAR

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Required EHCI state is maintained as a CAR_GLOBAL to have it
properly migrated.

Change-Id: I8df413bec6faae4952670710c8ac804e0331c966
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15236
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry-picked from commit 4b86314495)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354190
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-06-15 16:01:16 +03:00 • committed by chrome-bot
commit dad8bccd5a
1 changed files with 0 additions and 13 deletions
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13
src/soc/intel/broadwell/romstage/cache_as_ram.inc
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@ -26,7 +26,6 @@
(CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#define CACHE_AS_RAM_LIMIT (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)
#define USBDEBUG_VAR_SIZE 36 /* sizeof(struct ehci_debug_info) */
/* Cache 4GB - MRC_SIZE_KB for MRC */
#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
@ -166,9 +165,6 @@ clear_mtrrs:
/* Setup the stack. */
movl $(CACHE_AS_RAM_LIMIT), %eax
#if CONFIG_USBDEBUG
sub $(USBDEBUG_VAR_SIZE), %eax
#endif
movl %eax, %esp
/* Restore the BIST result. */
@ -193,15 +189,6 @@ before_romstage:
post_code(0x2f)
/* Copy global variable space (for USBDEBUG) to memory */
#if CONFIG_USBDEBUG
cld
movl $(CACHE_AS_RAM_LIMIT - USBDEBUG_VAR_SIZE), %esi
movl $(CONFIG_RAMTOP - USBDEBUG_VAR_SIZE), %edi
movl $USBDEBUG_VAR_SIZE, %ecx
rep movsb
#endif
post_code(0x30)
/* Disable cache. */