From 4eeefb31eddefb233f13db1bd375db216a9b9e1a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 16 Jun 2016 21:14:25 +0300 Subject: [PATCH] UPSTREAM: VIA C7 NANO: Fix early MTRR setting It would not be possible to set MTRR for range 1MiB to 4MiB. Our RAMTOP is power of 2 and enabling cache for bottom 1MiB should cause no problems. Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02 Original-Signed-off-by: Kysti Mlkki Original-Reviewed-on: https://review.coreboot.org/15238 Original-Reviewed-by: Aaron Durbin (cherry-picked from commit d71cfd204109b66aef0fe233e1e78e3c840fed6d) Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/354191 Tested-by: Furquan Shaikh Reviewed-by: Furquan Shaikh --- src/cpu/via/car/cache_as_ram.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 046d9c46d5..2f61b9138a 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -225,15 +225,15 @@ testok: movl $(MTRR_DEF_TYPE_EN), %eax wrmsr - /* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */ + /* Enable caching for 0..CONFIG_RAMTOP. */ movl $MTRR_PHYS_BASE(0), %ecx xorl %edx, %edx - movl $(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax + movl $(0x0 | MTRR_TYPE_WRBACK), %eax wrmsr movl $MTRR_PHYS_MASK(0), %ecx movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr /* Cache XIP_ROM area to speedup coreboot code. */