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mb/google/brox/variants/brox: Update PL1 Min

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Update PL1 Min value from 6W to 15W based on the brox thermal cooling
capacity and hardware design.

BUG=None
BRANCH=None
TEST=Build and boot on brox board

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I266a78806e065bf7af0d5fcad9b22ab63aa892e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sumeet Pawnikar 2024-07-23 11:54:30 +05:30 • committed by Felix Held
commit 4e1ed767ab
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/brox/variants/brox/ramstage.c
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@ -16,7 +16,7 @@ const struct cpu_power_limits performance_efficient_limits[] = {
{
.mchid = PCI_DID_INTEL_RPL_P_ID_3,
.cpu_tdp = 15,
.pl1_min_power = 6000,
.pl1_min_power = 15000,
.pl1_max_power = 15000,
.pl2_min_power = 55000,
.pl2_max_power = 55000,
@ -25,7 +25,7 @@ const struct cpu_power_limits performance_efficient_limits[] = {
{
.mchid = PCI_DID_INTEL_RPL_P_ID_4,
.cpu_tdp = 15,
.pl1_min_power = 6000,
.pl1_min_power = 15000,
.pl1_max_power = 15000,
.pl2_min_power = 55000,
.pl2_max_power = 55000,