From 4e1ed767ab26deccc7b1b65b5b556d693dd6053e Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Tue, 23 Jul 2024 11:54:30 +0530 Subject: [PATCH] mb/google/brox/variants/brox: Update PL1 Min Update PL1 Min value from 6W to 15W based on the brox thermal cooling capacity and hardware design. BUG=None BRANCH=None TEST=Build and boot on brox board Signed-off-by: Sumeet Pawnikar Change-Id: I266a78806e065bf7af0d5fcad9b22ab63aa892e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83661 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/google/brox/variants/brox/ramstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/brox/variants/brox/ramstage.c b/src/mainboard/google/brox/variants/brox/ramstage.c index c81dd7e8be..78e03caccb 100644 --- a/src/mainboard/google/brox/variants/brox/ramstage.c +++ b/src/mainboard/google/brox/variants/brox/ramstage.c @@ -16,7 +16,7 @@ const struct cpu_power_limits performance_efficient_limits[] = { { .mchid = PCI_DID_INTEL_RPL_P_ID_3, .cpu_tdp = 15, - .pl1_min_power = 6000, + .pl1_min_power = 15000, .pl1_max_power = 15000, .pl2_min_power = 55000, .pl2_max_power = 55000, @@ -25,7 +25,7 @@ const struct cpu_power_limits performance_efficient_limits[] = { { .mchid = PCI_DID_INTEL_RPL_P_ID_4, .cpu_tdp = 15, - .pl1_min_power = 6000, + .pl1_min_power = 15000, .pl1_max_power = 15000, .pl2_min_power = 55000, .pl2_max_power = 55000,