From 4b765fdd988615140ac743305361e96bf0aa24eb Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Wed, 30 Apr 2025 15:06:36 -0700 Subject: [PATCH] mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC This commit addresses a performance issue on the Panther Lake H SoC by disabling the EnableFastVmode setting in addition to the CepEnable setting. It was discovered that merely disabling CepEnable was insufficient, as the FSP continued to program Panther Lake U IccLimit on FastVMode capable boards, causing performance degradation under high-stress conditions. By also disabling EnableFastVmode, the I_TRIP value is prevented from being set lower than the device's actual capability. TEST=Verify that IccLimit is programmed with FSP default values. Change-Id: I2974f1311b69f283d7fa4982c28a9037a8ab23f7 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/87505 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Zhixing Ma --- src/mainboard/google/fatcat/romstage.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c index 44a901a0ec..7a509384b2 100644 --- a/src/mainboard/google/fatcat/romstage.c +++ b/src/mainboard/google/fatcat/romstage.c @@ -62,8 +62,10 @@ static void disable_vr_settings_on_pantherlake_h(FSP_M_CONFIG *m_cfg) * because the I_TRIP value is set lower than the device's actual capability. */ printk(BIOS_INFO, "Disabling VR settings on PTL-H.\n"); - for (size_t i = 0; i < NUM_VR_DOMAINS; i++) + for (size_t i = 0; i < NUM_VR_DOMAINS; i++) { m_cfg->CepEnable[i] = false; + m_cfg->EnableFastVmode[i] = false; + } } void mainboard_memory_init_params(FSPM_UPD *memupd)