From 4af27f02614da41c611aee2c6d175b1b948428ea Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 31 Jan 2014 16:31:49 -0800 Subject: [PATCH] nyan_big: apply cache-related changes from nyan This applies the same changes from 07a3592 that were applied to nyan. BUG=none BRANCH=none TEST=it compiles. Signed-off-by: David Hendricks Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c Reviewed-on: https://chromium-review.googlesource.com/184551 Commit-Queue: David Hendricks Tested-by: David Hendricks Reviewed-by: David Hendricks --- src/mainboard/google/nyan_big/romstage.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 0e7102093d..c013d11ea9 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -72,25 +72,12 @@ static void configure_l2actlr(void) write_l2actlr(val); } -void main(void) +static void __attribute__((noinline)) romstage(void) { #if CONFIG_COLLECT_TIMESTAMPS uint64_t romstage_start_time = timestamp_get(); #endif - // Globally disable MMU, caches and branch prediction (these should - // already be disabled by default on reset). - uint32_t sctlr = read_sctlr(); - sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I); - write_sctlr(sctlr); - - arm_invalidate_caches(); - - // Renable icache and branch prediction. - sctlr = read_sctlr(); - sctlr |= SCTLR_Z | SCTLR_I; - write_sctlr(sctlr); - configure_l2ctlr(); configure_l2actlr(); @@ -104,7 +91,6 @@ void main(void) CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); mmu_disable_range(0, 1); - dcache_invalidate_all(); dcache_mmu_enable(); /* For quality of the user experience, it's important to get @@ -140,3 +126,10 @@ void main(void) #endif stage_exit(entry); } + +/* Stub to force arm_init_caches to the top, before any stack/memory accesses */ +void main(void) +{ + asm ("bl arm_init_caches" ::: "r0","r1","r2","r3","r4","r5","ip"); + romstage(); +}