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UPSTREAM: soc/intel/skylake: use SPI flash boot_device_rw() for ealy stages

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If the boot device is SPI flash use the common one in the
early stages. While tweaking the config don't auto select
SPI_FLASH as that is handled automatically by the rest of the
build system.

CQ-DEPEND=CL:374981,CL:374980
BUG=chrome-os-partner:56151
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16202
Reviewed-by: Furquan Shaikh <furquan@google.com>

Change-Id: Ifd51a80fd008c336233d6e460c354190fcc0ef22
Reviewed-on: https://chromium-review.googlesource.com/373364
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Aaron Durbin 2016-08-11 23:55:39 -05:00 • committed by chrome-bot
commit 4987acd8a3
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/skylake/Kconfig
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@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select ACPI_NHLT
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
@ -46,7 +47,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_RESET
select SMM_TSEG
select SMP
select SPI_FLASH
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_CONSTANT_RATE