UPSTREAM: soc/intel/skylake: align chromium Chrome OS config

The chromium tree is currently using a different config for
Chrome OS than what is being built in coreboot.org. Align those
settings to reflect how skylake Chrome OS boards are actually
shipped to provide proper parity between coreboot.org and chromium.

CQ-DEPEND=CL:374980,CL:37336
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16313
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I7ab9c1dfa8c6be03ac2125fb06cb7022f3befa97
Reviewed-on: https://chromium-review.googlesource.com/374981
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/skylake/Kconfig

@@ -56,9 +56,11 @@ config CPU_SPECIFIC_OPTIONS
 config CHROMEOS
 	select CHROMEOS_RAMOOPS_DYNAMIC
 	select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC
+	select SEPARATE_VERSTAGE
 	select VBOOT_EC_SLOW_UPDATE
 	select VBOOT_OPROM_MATTERS
 	select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
+	select VBOOT_STARTS_IN_BOOTBLOCK
 	select VBOOT_VBNV_CMOS
 	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 	select VIRTUAL_DEV_SWITCH

src/soc/intel/skylake/Makefile.inc

@@ -28,6 +28,7 @@ bootblock-y += pmutil.c
 bootblock-y += tsc_freq.c
 
 verstage-y += flash_controller.c
+verstage-y += monotonic_timer.c
 verstage-y += pch.c
 verstage-$(CONFIG_UART_DEBUG) += uart_debug.c