From 4987acd8a33072bcd3f50fa064a98c5865fcbfe7 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 11 Aug 2016 23:55:39 -0500 Subject: [PATCH] UPSTREAM: soc/intel/skylake: use SPI flash boot_device_rw() for ealy stages If the boot device is SPI flash use the common one in the early stages. While tweaking the config don't auto select SPI_FLASH as that is handled automatically by the rest of the build system. CQ-DEPEND=CL:374981,CL:374980 BUG=chrome-os-partner:56151 BRANCH=None TEST=None Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/16202 Reviewed-by: Furquan Shaikh Change-Id: Ifd51a80fd008c336233d6e460c354190fcc0ef22 Reviewed-on: https://chromium-review.googlesource.com/373364 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ef3f156da2..6171c41b27 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select ACPI_NHLT + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE @@ -46,7 +47,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SMM_TSEG select SMP - select SPI_FLASH select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_CONSTANT_RATE