From 4772d019f340c74a8cb1abb8907ccd59da17e86c Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 26 Jan 2026 07:36:20 +0100 Subject: [PATCH] soc/intel/apollolake: Align MPinit code Align the MPinit code with other Intel CPU drivers and move the microcode update on the BSP to pre_mp_init(). This also ensures that the microcode is located in CBFS before the MTRRs are set up using x86_setup_mtrrs_with_detect() which removes caching the SPI flash MMIO area. No functional change, thus untested. Signed-off-by: Patrick Rudolph Change-Id: I47573dde5d471c9654ea9f14bd24b2a7087dd6df Reviewed-on: https://review.coreboot.org/c/coreboot/+/90909 Tested-by: build bot (Jenkins) Reviewed-by: Sean Rhodes Reviewed-by: Paul Menzel --- src/soc/intel/apollolake/cpu.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index fb95009f7d..67450b2d5d 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -162,6 +162,11 @@ static void pre_mp_init(void) fsps_load(); return; } + + /* Make sure BSP is using the microcode from cbfs */ + const struct microcode *microcode_patch = intel_microcode_find(); + intel_microcode_load_unlocked(microcode_patch); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); } @@ -192,9 +197,6 @@ void get_microcode_info(const void **microcode, int *parallel) { *microcode = intel_microcode_find(); *parallel = 1; - - /* Make sure BSP is using the microcode from cbfs */ - intel_microcode_load_unlocked(*microcode); } #endif