From 46df9e1d38f638f66be092fc8ec64a118581b0b5 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 13 Dec 2024 01:40:44 +0530 Subject: [PATCH] mb/google/brya/var/marasov: Enable GPP_F9 GPIO for early panel power-on This change enables the GPP_F9 GPIO, which controls the SLP_S0_GATE_R signal and subsequently the SYS_SLP_S0IX_L signal. By enabling GPP_F9 early in the boot process, we ensure the panel is powered on correctly and able to render the eSOL message. BUG=b:372737590 TEST=Verified panel power-on by observing eSOL during build on google/marasov. Change-Id: I727a72d9583575b2bbebe2c3b75c980170dd36b9 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/85574 Tested-by: build bot (Jenkins) Reviewed-by: Dinesh Gehlot Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal Reviewed-by: Nick Vaccaro --- src/mainboard/google/brya/variants/marasov/gpio.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/google/brya/variants/marasov/gpio.c b/src/mainboard/google/brya/variants/marasov/gpio.c index 15760fdc2a..3c6f638899 100644 --- a/src/mainboard/google/brya/variants/marasov/gpio.c +++ b/src/mainboard/google/brya/variants/marasov/gpio.c @@ -2,6 +2,7 @@ #include #include +#include #include /* Pad configuration in ramstage */ @@ -222,6 +223,17 @@ static const struct pad_config romstage_gpio_table[] = { PAD_CFG_GPO(GPP_D2, 0, DEEP), }; +static const struct pad_config early_graphics_gpio_table[] = { + /* F9 : BOOTMPC ==> SLP_S0_GATE_R */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), +}; + +const struct pad_config *variant_early_graphics_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_graphics_gpio_table); + return early_graphics_gpio_table; +} + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table);