From 418337a5bde70df6a770222201c51bf3e8892d5f Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Wed, 18 Dec 2013 22:35:16 -0800 Subject: [PATCH] tegra124: use pll_c_out1 as sclk parent The kernel does not support using pll_c_out0 as the parent of sclk, nor does it support the use of super dividers. The reason for this is that DVFS schemes must use the pre-divided rate with using super dividers when setting voltages, which makes them essentially useless. Instead, set pll_c_out1 to 300Mhz (pll_c / 2) and use that as the parent of sclk. BUG=chrome-os-partner:24487 TEST=Kernel now boots with sclk DVFS enabled BRANCH=None Change-Id: Ia106963d290122cddbaf9eaf88047fda2dfe8b8a Signed-off-by: Andrew Bresticker Reviewed-on: https://chromium-review.googlesource.com/180865 Reviewed-by: Dylan Reid Reviewed-by: David Hendricks Reviewed-by: Jimmy Zhang --- src/soc/nvidia/tegra124/clock.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 998a82c87d..26e25f963b 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -401,11 +401,10 @@ void clock_init(void) * features section in the TRM). */ write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT, &clk_rst->clk_sys_rate); /* pclk = hclk = sclk/2 */ - write32(0 << SCLK_DIVIDEND_SHIFT | - (div_round_up(TEGRA_PLLC_KHZ, 300000) - 1) << SCLK_DIVISOR_SHIFT - | SCLK_DIV_ENB, &clk_rst->super_sclk_div); + write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_CLKEN | PLL_OUT_RSTN, &clk_rst->pllc_out); write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | - SCLK_SOURCE_PLLC_OUT0 << SCLK_RUN_SHIFT, + SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT, &clk_rst->sclk_brst_pol); /* sclk = 300 MHz */ /* Change the oscillator drive strength (from U-Boot -- why?) */