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urara: UART: line control setting configuration added: 8bit, 1 stop bit, no parity

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BUG=chrome-os-partner:31438
TEST=built urara bootblock and ran it on the Pistachio FPGA, observed
      expected console output.
BRANCH=none

Change-Id: I14fe343c98b11774b93b2724b6bffa3b45ea17b4
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://chromium-review.googlesource.com/226551
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
This commit is contained in:
Ionela Voinescu 2014-10-30 14:49:53 +00:00 • committed by chrome-internal-fetch
commit 4122ae983d
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/urara/Kconfig
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@ -43,4 +43,8 @@ config DRAM_SIZE_MB
int
default 256
config TTYS0_LCS
int
default 3
endif