From 4122ae983dba907c10d0d0980863ae7bf94eda5e Mon Sep 17 00:00:00 2001
From: Ionela Voinescu <ionela.voinescu@imgtec.com>
Date: Thu, 30 Oct 2014 14:49:53 +0000
Subject: [PATCH] urara: UART: line control setting configuration added: 8bit,
 1 stop bit, no parity

BUG=chrome-os-partner:31438
TEST=built urara bootblock and ran it on the Pistachio FPGA, observed
      expected console output.
BRANCH=none

Change-Id: I14fe343c98b11774b93b2724b6bffa3b45ea17b4
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://chromium-review.googlesource.com/226551
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
---
 src/mainboard/google/urara/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig
index fa9d7bb42a..0020ebbea1 100644
--- a/src/mainboard/google/urara/Kconfig
+++ b/src/mainboard/google/urara/Kconfig
@@ -43,4 +43,8 @@ config DRAM_SIZE_MB
 	int
 	default 256
 
+config TTYS0_LCS
+	int
+	default 3
+
 endif