diff --git a/src/mainboard/intel/ptlrvp/chromeos.fmd b/src/mainboard/intel/ptlrvp/chromeos.fmd
index 693f485e4a..852fba0bab 100644
--- a/src/mainboard/intel/ptlrvp/chromeos.fmd
+++ b/src/mainboard/intel/ptlrvp/chromeos.fmd
@@ -1,20 +1,17 @@
 FLASH 32M {
-	SI_ALL 8M {
+	SI_ALL 18M {
 		SI_DESC 16K
 		SI_EC 576K
 		SI_ME
+		SI_ME_PAD@16M 2M
 	}
-	SI_BIOS 24M {
-		RW_SECTION_A 8M {
+	SI_BIOS 14M {
+		RW_SECTION_A 4M {
 			VBLOCK_A 8K
 			FW_MAIN_A(CBFS)
 			RW_FWID_A 64
 		}
-		# This section starts at the 16M boundary in SPI flash.
-		# PTL does not support a region crossing this boundary,
-		# because the SPI flash is memory-mapped into two non-
-		# contiguous windows.
-		RW_SECTION_B 8M {
+		RW_SECTION_B 4M {
 			VBLOCK_B 8K
 			FW_MAIN_B(CBFS)
 			RW_FWID_B 64
@@ -33,7 +30,6 @@ FLASH 32M {
 			RW_NVRAM(PRESERVE) 24K
 		}
 		RW_LEGACY(CBFS) 1M
-		RW_UNUSED 2M
 		# Make WP_RO region align with SPI vendor
 		# memory protected range specification.
 		WP_RO 4M {