From 3d4c77c7f434d430370fc3867e406880f0e1dff1 Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Tue, 3 Feb 2026 18:45:54 +0530 Subject: [PATCH] soc/intel/pantherlake: Set CONFIG_MAX_ROOT_PORTS to 12 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Increase the maximum root port count for Panther Lake (PTL) to 12. While the actual number of active ports may vary depending on the specific SKU and strapping, setting this constant to 12 is safe and systematically handled by the existing SoC logic. Systematic Bounds: The common PCIe root port driver (pcie_rp.c) and PTL-specific FSP parameter logic utilize ptl_rp_groups and PCI configuration space accesses to determine the actual hardware limits at runtime. Safe Ceiling: CONFIG_MAX_ROOT_PORTS serves as a compile-time upper bound for array allocations and iteration loops. Setting this to 12 accommodates the maximum possible PTL configuration without over-allocating resources. Consistency: This aligns the configuration with the hardware's maximum capability, allowing the silicon initialization code to dynamically "fill in" the details for lower-port SKUs without requiring further Kconfig changes. BUG=None TEST=Able to build boards that use different PTL SKUs. Change-Id: Icb8f2c075aa56531e311d1ce718953fe3366a5e2 Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/91078 Reviewed-by: Alicja Michalska Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 59369a6a46..92397037af 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -253,7 +253,6 @@ config MAX_TBT_ROOT_PORTS config MAX_ROOT_PORTS int default 6 if SOC_INTEL_WILDCATLAKE - default 10 if SOC_INTEL_PANTHERLAKE_H default 12 config MAX_PCIE_CLOCK_SRC