From 3a33217349b4f2e43de758c10e947729b0bb50d9 Mon Sep 17 00:00:00 2001 From: Hualin Wei Date: Mon, 22 Sep 2025 20:21:23 +0800 Subject: [PATCH] mb/google/fatcat/var/lapis: Update thermal strategy According to the schematic diagram, lapis is designed with five temperature detection nodes, so the initial thermal strategy was updated. BUG=b:438785495 TEST=emerge-fatcat coreboot Change-Id: I908ab68766ef562ecc95085ed21658f3592937f4 Signed-off-by: Hualin Wei Reviewed-on: https://review.coreboot.org/c/coreboot/+/89068 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Pranava Y N --- .../fatcat/variants/lapis/overridetree.cb | 31 ++++++++++++++----- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb index cf2ad628fa..f86cf47a79 100644 --- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb @@ -65,10 +65,11 @@ chip soc/intel/pantherlake device ref dtt on chip drivers/intel/dptf ## sensor information - register "options.tsr[0].desc" = ""DDR_SOC"" - register "options.tsr[1].desc" = ""Ambient"" - register "options.tsr[2].desc" = ""Charger"" - register "options.tsr[3].desc" = ""wwan"" + register "options.tsr[0].desc" = ""VR"" + register "options.tsr[1].desc" = ""DDR"" + register "options.tsr[2].desc" = ""Top"" + register "options.tsr[3].desc" = ""SSD"" + register "options.tsr[4].desc" = ""Charger"" ## Active Policy # FIXME: below values are initial reference values only @@ -108,6 +109,18 @@ chip soc/intel/pantherlake }, [3] = { .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + }, + [4] = { + .target = DPTF_TEMP_SENSOR_4, .thresholds = { TEMP_PCT(75, 90), TEMP_PCT(70, 80), @@ -128,16 +141,18 @@ chip soc/intel/pantherlake [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000), [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 80, 5000), + [5] = DPTF_PASSIVE(CPU, TEMP_SENSOR_4, 80, 5000), }" ## Critical Policy # TODO: below values are initial reference values only register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), - [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), - [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 91, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 91, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 91, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 91, SHUTDOWN), + [5] = DPTF_CRITICAL(TEMP_SENSOR_4, 91, SHUTDOWN), }" ## Power Limits Control