From 391d5f3cb4bae451dfe7ace9c4ad4e633027e51a Mon Sep 17 00:00:00 2001 From: Varun Upadhyay Date: Wed, 18 Feb 2026 16:11:33 +0530 Subject: [PATCH] mb/google/ocelot/var/ojal: Enable dtt and ish based on FW config This patch enables dtt and ish in devicetree for ojal and updates FW config for GPIO's config according to schematics revision 0.9. RDC kit no:840138 BUG=b:437459757 TEST=Build ojal board and check dmesg for errors. Change-Id: If2ece13575ebad661cc7de78e77e3bf2f30e69e1 Signed-off-by: Varun Upadhyay Reviewed-on: https://review.coreboot.org/c/coreboot/+/91334 Tested-by: build bot (Jenkins) Reviewed-by: Aralguppe, Sowmya Reviewed-by: Bhat D, Krishna P --- .../google/ocelot/variants/ojal/fw_config.c | 36 +++++ .../ocelot/variants/ojal/overridetree.cb | 139 ++++++++++++++++++ 2 files changed, 175 insertions(+) diff --git a/src/mainboard/google/ocelot/variants/ojal/fw_config.c b/src/mainboard/google/ocelot/variants/ojal/fw_config.c index 39762a967c..a0e1f60ecc 100644 --- a/src/mainboard/google/ocelot/variants/ojal/fw_config.c +++ b/src/mainboard/google/ocelot/variants/ojal/fw_config.c @@ -142,6 +142,36 @@ static const struct pad_config cnvi_disable_pads[] = { PAD_NC(GPP_F05, NONE), }; +static const struct pad_config ish_disable_pads[] = { + /* GPP_B06: C_EC_ISH_ALRT */ + PAD_NC(GPP_B06, NONE), + /* GPP_B07: SLATEMODE_HALLOUT_SNSR_R */ + PAD_NC(GPP_B07, NONE), + /* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */ + PAD_NC(GPP_B18, NONE), + /* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */ + PAD_NC(GPP_B19, NONE), + /* GPP_B23: ISH_GP_6_SNSR_HDR */ + PAD_NC(GPP_B23, NONE), + /* GPP_D06: ISH_UART0_ECAIC_TXD */ + PAD_NC(GPP_D06, NONE), +}; + +static const struct pad_config ish_enable_pads[] = { + /* GPP_B06: C_EC_ISH_ALRT */ + PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4), + /* GPP_B07: SLATEMODE_HALLOUT_SNSR_R */ + PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4), + /* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1), + /* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1), + /* GPP_B23: ISH_GP_6_SNSR_HDR */ + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4), + /* GPP_D06: ISH_UART0_ECAIC_TXD */ + PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2), +}; + static const struct pad_config touchpad_lpss_i2c_enable_pads[] = { /* GPP_H20: SOC_I2C_0_SCL */ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), @@ -265,6 +295,12 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads); } + if (fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) { + GPIO_PADBASED_OVERRIDE(padbased_table, ish_enable_pads); + } else { + GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads); + } + if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) { GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads); } else { diff --git a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb index adb8ece6a1..b548c3c468 100644 --- a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb @@ -38,6 +38,11 @@ end chip soc/intel/pantherlake + register "power_limits_config[WCL_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 35, + }" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1 register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port @@ -129,6 +134,132 @@ chip soc/intel/pantherlake device ref iaa off end + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""wwan"" + + ## Active Policy + # FIXME: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(70, 97), + TEMP_PCT(65, 90), + TEMP_PCT(60, 80), + TEMP_PCT(55, 75), + TEMP_PCT(50, 65), + TEMP_PCT(45, 45), + TEMP_PCT(43, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(70, 97), + TEMP_PCT(65, 90), + TEMP_PCT(60, 80), + TEMP_PCT(55, 75), + TEMP_PCT(50, 65), + TEMP_PCT(45, 45), + TEMP_PCT(43, 30), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 50), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + } + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 80, 5000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 95000, + .max_power = 95000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "true" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end device ref tcss_xhci on @@ -163,6 +294,14 @@ chip soc/intel/pantherlake end end + device ref ish on + probe ISH ISH_ENABLE + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref xhci on chip drivers/usb/acpi device ref xhci_root_hub on