From 36d2dc7cb95e3a130f3c6f92028f281ce1d34d14 Mon Sep 17 00:00:00 2001 From: Sowmya Aralguppe Date: Mon, 22 Sep 2025 11:18:21 +0530 Subject: [PATCH] mb/google/ocelot: Update wake event mapping for gspi0 This change corrects the ACPI wake event mapping for the gspi0 device, ensuring the wake signal is routed through GPE0_DW2_19 instead of GPE0_DW1_19. This aligns with the platform's GPIO-to-GPE mapping in devicetree.cb Change-Id: I2c9b0168c01c4ff8f968f0efe5bc12b650842129 Signed-off-by: Sowmya Aralguppe Reviewed-on: https://review.coreboot.org/c/coreboot/+/89287 Tested-by: build bot (Jenkins) Reviewed-by: Avi Uday Reviewed-by: Pranava Y N --- src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb index d7564f4602..8867ca2178 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb @@ -541,7 +541,7 @@ chip soc/intel/pantherlake register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E19_IRQ)" - register "wake" = "GPE0_DW1_19" + register "wake" = "GPE0_DW2_19" register "has_power_resource" = "true" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E05)"