diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index afd74ee23a..d1880e4299 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -9,8 +9,8 @@
 #include <framebuffer_info.h>
 #include <soc/ddp.h>
 #include <soc/display.h>
+#include <soc/display_dsi.h>
 #include <soc/dptx.h>
-#include <soc/dsi.h>
 #include <soc/mtcmos.h>
 #include <stdio.h>
 #include <symbols.h>
diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c
index f9e7e2954b..66a5aaf2e1 100644
--- a/src/soc/mediatek/common/dsi_common.c
+++ b/src/soc/mediatek/common/dsi_common.c
@@ -5,6 +5,7 @@
 #include <device/mmio.h>
 #include <delay.h>
 #include <edid.h>
+#include <soc/display_dsi.h>
 #include <soc/dsi.h>
 #include <string.h>
 #include <timer.h>
diff --git a/src/soc/mediatek/common/include/soc/display_dsi.h b/src/soc/mediatek/common/include/soc/display_dsi.h
new file mode 100644
index 0000000000..62bdb3cca3
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/display_dsi.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_DISPLAY_DSI_H
+#define SOC_MEDIATEK_DISPLAY_DSI_H
+
+#include <edid.h>
+#include <types.h>
+
+enum mipi_dsi_pixel_format {
+	MIPI_DSI_FMT_RGB888,
+	MIPI_DSI_FMT_RGB666,
+	MIPI_DSI_FMT_RGB666_PACKED,
+	MIPI_DSI_FMT_RGB565
+};
+
+/* video mode */
+enum {
+	MIPI_DSI_MODE_VIDEO = BIT(0),
+	/* video burst mode */
+	MIPI_DSI_MODE_VIDEO_BURST = BIT(1),
+	/* video pulse mode */
+	MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2),
+	/* enable auto vertical count mode */
+	MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3),
+	/* enable hsync-end packets in vsync-pulse and v-porch area */
+	MIPI_DSI_MODE_VIDEO_HSE = BIT(4),
+	/* disable hfront-porch area */
+	MIPI_DSI_MODE_VIDEO_HFP = BIT(5),
+	/* disable hback-porch area */
+	MIPI_DSI_MODE_VIDEO_HBP = BIT(6),
+	/* disable hsync-active area */
+	MIPI_DSI_MODE_VIDEO_HSA = BIT(7),
+	/* flush display FIFO on vsync pulse */
+	MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8),
+	/* disable EoT packets in HS mode */
+	MIPI_DSI_MODE_EOT_PACKET = BIT(9),
+	/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
+	MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
+	/* transmit data in low power */
+	MIPI_DSI_MODE_LPM = BIT(11),
+	/* dsi per line's data end same time on all lanes */
+	MIPI_DSI_MODE_LINE_END = BIT(12),
+	/* mipi is in CPHY mode */
+	MIPI_DSI_MODE_CPHY = BIT(13),
+	/* mipi is DSI Dual Channel mode */
+	MIPI_DSI_DUAL_CHANNEL = BIT(14),
+	/* mipi is DSC compression mode */
+	MIPI_DSI_DSC_MODE = BIT(15),
+};
+
+/* Public API for common display code (display.c). */
+int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
+		 const u8 *init_commands);
+
+#endif /* SOC_MEDIATEK_DISPLAY_DSI_H */
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index a21929809f..83f6254777 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -8,48 +8,7 @@
 #include <mipi/dsi.h>
 #include <types.h>
 #include <soc/addressmap.h>
-
-enum mipi_dsi_pixel_format {
-	MIPI_DSI_FMT_RGB888,
-	MIPI_DSI_FMT_RGB666,
-	MIPI_DSI_FMT_RGB666_PACKED,
-	MIPI_DSI_FMT_RGB565
-};
-
-/* video mode */
-enum {
-	MIPI_DSI_MODE_VIDEO = BIT(0),
-	/* video burst mode */
-	MIPI_DSI_MODE_VIDEO_BURST = BIT(1),
-	/* video pulse mode */
-	MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2),
-	/* enable auto vertical count mode */
-	MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3),
-	/* enable hsync-end packets in vsync-pulse and v-porch area */
-	MIPI_DSI_MODE_VIDEO_HSE = BIT(4),
-	/* disable hfront-porch area */
-	MIPI_DSI_MODE_VIDEO_HFP = BIT(5),
-	/* disable hback-porch area */
-	MIPI_DSI_MODE_VIDEO_HBP = BIT(6),
-	/* disable hsync-active area */
-	MIPI_DSI_MODE_VIDEO_HSA = BIT(7),
-	/* flush display FIFO on vsync pulse */
-	MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8),
-	/* disable EoT packets in HS mode */
-	MIPI_DSI_MODE_EOT_PACKET = BIT(9),
-	/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
-	MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
-	/* transmit data in low power */
-	MIPI_DSI_MODE_LPM = BIT(11),
-	/* dsi per line's data end same time on all lanes */
-	MIPI_DSI_MODE_LINE_END = BIT(12),
-	/* mipi is in CPHY mode */
-	MIPI_DSI_MODE_CPHY = BIT(13),
-	/* mipi is DSI Dual Channel mode */
-	MIPI_DSI_DUAL_CHANNEL = BIT(14),
-	/* mipi is DSC compression mode */
-	MIPI_DSI_DSC_MODE = BIT(15),
-};
+#include <soc/display_dsi.h>
 
 static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;
 
@@ -209,8 +168,8 @@ void mtk_dsi_reset(void);
 void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing);
 
 /*
- * Public API provided in common/dsi_common.c, common/dsi_v1.c, and
- * common/mtk_mipi_{c/d}phy.c
+ * DSI-internal APIs provided in common/dsi_common.c, common/dsi_v1.c,
+ * and common/mtk_mipi_{c/d}phy.c
  */
 void mtk_dsi_cphy_enable(void);
 void mtk_dsi_cphy_enable_cmdq_6byte(void);
@@ -224,7 +183,5 @@ void mtk_dsi_cphy_disable_ck_mode(void);
 void mtk_dsi_dphy_disable_ck_mode(void);
 void mtk_dsi_dphy_timing_calculation(u32 data_rate_mhz, struct mtk_phy_timing *timing);
 void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy);
-int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
-		 const u8 *init_commands);
 
 #endif /* SOC_MEDIATEK_DSI_COMMON_H */
diff --git a/src/soc/mediatek/mt8195/include/soc/dsi.h b/src/soc/mediatek/mt8195/include/soc/dsi.h
deleted file mode 100644
index 0fd65b93f8..0000000000
--- a/src/soc/mediatek/mt8195/include/soc/dsi.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_MEDIATEK_MT8195_DSI_H
-#define SOC_MEDIATEK_MT8195_DSI_H
-
-#include <soc/dsi_common.h>
-
-#endif