From 360678f79a9c578325e902cb2b4c290e4808188c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 15 Apr 2025 19:53:37 +0100
Subject: [PATCH] soc/intel/cnvi: Correct value of CNVI_ABORT_PLDR
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The definitions were reversed, as PCH_S should use 0x44, and all others
0x80.

These values can be seen in SlimBootloader, and most UEFI firmwares.

Change-Id: Ia2e3866ef7d0756220f15a8d2bdf639ac6667738
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87323
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/common/block/include/intelblocks/cnvi.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/include/intelblocks/cnvi.h b/src/soc/intel/common/block/include/intelblocks/cnvi.h
index fa96fdd37d..52f9238206 100644
--- a/src/soc/intel/common/block/include/intelblocks/cnvi.h
+++ b/src/soc/intel/common/block/include/intelblocks/cnvi.h
@@ -15,9 +15,9 @@
 
 /* CNVi PLDR Control */
 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
-#define CNVI_ABORT_PLDR		0x80
-#else
 #define CNVI_ABORT_PLDR		0x44
+#else
+#define CNVI_ABORT_PLDR		0x80
 #endif
 
 #define CNVI_ABORT_ENABLE	BIT(0)