diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index e5c98c412c..f7ff7761a9 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -26,7 +26,7 @@ chip soc/intel/alderlake
 	# Refer to EDS-Vol2-42.3.8.
 	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
 	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
-	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x311b"
 
 	# EMMC TX DATA Delay 2
 	# Refer to EDS-Vol2-42.3.9.
@@ -34,7 +34,7 @@ chip soc/intel/alderlake
 	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
 	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
 	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
-	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C282928"
 
 	# EMMC RX CMD/DATA Delay 1
 	# Refer to EDS-Vol2-42.3.10.
@@ -42,7 +42,7 @@ chip soc/intel/alderlake
 	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
 	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
 	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
-	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C19593B"
 
 	# EMMC RX CMD/DATA Delay 2
 	# Refer to EDS-Vol2-42.3.12.
@@ -53,13 +53,13 @@ chip soc/intel/alderlake
 	#         11: Reserved
 	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
 	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
-	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E"
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10026"
 
 	# EMMC Rx Strobe Delay
 	# Refer to EDS-Vol2-42.3.11.
 	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
 	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
-	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
+	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01313"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1