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lynxpoint: Don't write to non-existent EHCI

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The LynxPoint-LP chipset only has one EHCI controller so we should
not attempt to write into the second one that only exists on LynxPoint-H.

BUG=chrome-os-partner:21342
BRANCH=falco,peppy
TEST=emerge-falco chromeos-coreboot-falco

Change-Id: I1eae060c7f0a5873c9684e5abfeea5cb5895ab62
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2013-07-30 15:45:25 -07:00 • committed by ChromeBot
commit 2abf25d5f1
2 changed files with 13 additions and 5 deletions
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6
src/southbridge/intel/lynxpoint/early_pch.c
View file

@ -41,6 +41,12 @@ const struct rcba_config_instruction pch_early_config[] = {
RCBA_END_CONFIG,
};
int pch_is_lp(void)
{
u8 id = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
return id == PCH_TYPE_LPT_LP;
}
static void pch_enable_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */

12
src/southbridge/intel/lynxpoint/early_usb.c
View file

@ -48,9 +48,11 @@ void enable_usb_bar(void)
pci_write_config32(usb0, PCI_COMMAND, cmd);
/* USB Controller 1 */
pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
PCH_EHCI1_TEMP_BAR0);
cmd = pci_read_config32(usb1, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb1, PCI_COMMAND, cmd);
if (!pch_is_lp()) {
pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
PCH_EHCI2_TEMP_BAR0);
cmd = pci_read_config32(usb1, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb1, PCI_COMMAND, cmd);
}
}