From 2abf25d5f196fda333d12f6900e6c9b44d8c83c8 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 30 Jul 2013 15:45:25 -0700 Subject: [PATCH] lynxpoint: Don't write to non-existent EHCI The LynxPoint-LP chipset only has one EHCI controller so we should not attempt to write into the second one that only exists on LynxPoint-H. BUG=chrome-os-partner:21342 BRANCH=falco,peppy TEST=emerge-falco chromeos-coreboot-falco Change-Id: I1eae060c7f0a5873c9684e5abfeea5cb5895ab62 Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/63799 Reviewed-by: Aaron Durbin --- src/southbridge/intel/lynxpoint/early_pch.c | 6 ++++++ src/southbridge/intel/lynxpoint/early_usb.c | 12 +++++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 7367d07db7..df7358e04d 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -41,6 +41,12 @@ const struct rcba_config_instruction pch_early_config[] = { RCBA_END_CONFIG, }; +int pch_is_lp(void) +{ + u8 id = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1); + return id == PCH_TYPE_LPT_LP; +} + static void pch_enable_bars(void) { /* Setting up Southbridge. In the northbridge code. */ diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index ebd5c2c50a..24b991bac7 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -48,9 +48,11 @@ void enable_usb_bar(void) pci_write_config32(usb0, PCI_COMMAND, cmd); /* USB Controller 1 */ - pci_write_config32(usb1, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); - cmd = pci_read_config32(usb1, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb1, PCI_COMMAND, cmd); + if (!pch_is_lp()) { + pci_write_config32(usb1, PCI_BASE_ADDRESS_0, + PCH_EHCI2_TEMP_BAR0); + cmd = pci_read_config32(usb1, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(usb1, PCI_COMMAND, cmd); + } }