diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 7367d07db7..df7358e04d 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -41,6 +41,12 @@ const struct rcba_config_instruction pch_early_config[] = {
 	RCBA_END_CONFIG,
 };
 
+int pch_is_lp(void)
+{
+	u8 id = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
+	return id == PCH_TYPE_LPT_LP;
+}
+
 static void pch_enable_bars(void)
 {
 	/* Setting up Southbridge. In the northbridge code. */
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
index ebd5c2c50a..24b991bac7 100644
--- a/src/southbridge/intel/lynxpoint/early_usb.c
+++ b/src/southbridge/intel/lynxpoint/early_usb.c
@@ -48,9 +48,11 @@ void enable_usb_bar(void)
 	pci_write_config32(usb0, PCI_COMMAND, cmd);
 
 	/* USB Controller 1 */
-	pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
-			   PCH_EHCI1_TEMP_BAR0);
-	cmd = pci_read_config32(usb1, PCI_COMMAND);
-	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config32(usb1, PCI_COMMAND, cmd);
+	if (!pch_is_lp()) {
+		pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
+				   PCH_EHCI2_TEMP_BAR0);
+		cmd = pci_read_config32(usb1, PCI_COMMAND);
+		cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+		pci_write_config32(usb1, PCI_COMMAND, cmd);
+	}
 }