From 2a2595067077cd918bfd48cad79a684b8e1ff0f4 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 1 May 2014 08:48:32 -0700 Subject: [PATCH] broadwell: Split SMM related defines/prototypes to new header This puts all the SMM related information into one location instead of being split across several headers. BUG=chrome-os-partner:28234 TEST=None Change-Id: If4782d37f28b325ff76dd8efa560840d4e1da276 Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/198738 Reviewed-by: Aaron Durbin --- src/soc/intel/broadwell/broadwell/cpu.h | 23 ------ src/soc/intel/broadwell/broadwell/pch.h | 8 -- src/soc/intel/broadwell/broadwell/smm.h | 73 +++++++++++++++++++ .../intel/broadwell/broadwell/systemagent.h | 8 -- src/soc/intel/broadwell/smmrelocate.c | 20 +---- 5 files changed, 76 insertions(+), 56 deletions(-) create mode 100644 src/soc/intel/broadwell/broadwell/smm.h diff --git a/src/soc/intel/broadwell/broadwell/cpu.h b/src/soc/intel/broadwell/broadwell/cpu.h index b4e90662fc..ab1bb07c3f 100644 --- a/src/soc/intel/broadwell/broadwell/cpu.h +++ b/src/soc/intel/broadwell/broadwell/cpu.h @@ -134,26 +134,6 @@ /* Data is passed through bits 31:0 of the data register. */ #define BIOS_MAILBOX_DATA 0x5da0 -/* Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. */ -#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE -#define RESERVED_SMM_OFFSET \ - (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE) - -/* Sanity check config options. */ -#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)) -# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)" -#endif -#if (CONFIG_SMM_TSEG_SIZE < 0x800000) -# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" -#endif -#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) -# error "CONFIG_SMM_TSEG_SIZE is not a power of 2" -#endif -#if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0) -# error "CONFIG_IED_REGION_SIZE is not a power of 2" -#endif - #if !defined(__ROMCC__) // FIXME romcc should handle below constructs #if defined(__PRE_RAM__) @@ -196,9 +176,6 @@ void intel_cpu_haswell_finalize_smm(void); /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -/* Returns 0 on success, < 0 on failure. */ -int smm_initialize(void); -void smm_relocate(void); struct bus; void bsp_init_and_start_aps(struct bus *cpu_bus); /* Determine if HyperThreading is disabled. The variable is not valid until diff --git a/src/soc/intel/broadwell/broadwell/pch.h b/src/soc/intel/broadwell/broadwell/pch.h index b7c96e051c..c38753e5b6 100644 --- a/src/soc/intel/broadwell/broadwell/pch.h +++ b/src/soc/intel/broadwell/broadwell/pch.h @@ -60,14 +60,6 @@ void pch_log_state(void); void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -/* These helpers are for performing SMM relocation. */ -void southbridge_trigger_smi(void); -void southbridge_clear_smi_status(void); -/* The initialization of the southbridge is split into 2 compoments. One is - * for clearing the state in the SMM registers. The other is for enabling - * SMIs. They are split so that other work between the 2 actions. */ -void southbridge_smm_clear_state(void); -void southbridge_smm_enable_smi(void); #else void enable_smbus(void); void enable_usb_bar(void); diff --git a/src/soc/intel/broadwell/broadwell/smm.h b/src/soc/intel/broadwell/broadwell/smm.h new file mode 100644 index 0000000000..a6d896f042 --- /dev/null +++ b/src/soc/intel/broadwell/broadwell/smm.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BROADWELL_SMM_H_ +#define _BROADWELL_SMM_H_ + +#include +#include + +struct ied_header { + char signature[10]; + u32 size; + u8 reserved[34]; +} __attribute__ ((packed)); + +struct smm_relocation_params { + u32 smram_base; + u32 smram_size; + u32 ied_base; + u32 ied_size; + msr_t smrr_base; + msr_t smrr_mask; + msr_t emrr_base; + msr_t emrr_mask; + msr_t uncore_emrr_base; + msr_t uncore_emrr_mask; + /* The smm_save_state_in_msrs field indicates if SMM save state + * locations live in MSRs. This indicates to the CPUs how to adjust + * the SMMBASE and IEDBASE */ + int smm_save_state_in_msrs; +}; + +/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig + * is included after chipset code. This causes the chipset's Kconfig to be + * cloberred by the arch/x86/Kconfig if they have the same name. */ +static inline int smm_region_size(void) +{ + /* Make it 8MiB by default. */ + if (CONFIG_SMM_TSEG_SIZE == 0) + return (8 << 20); + return CONFIG_SMM_TSEG_SIZE; +} + +int smm_initialize(void); +void smm_relocate(void); + +/* These helpers are for performing SMM relocation. */ +void southbridge_trigger_smi(void); +void southbridge_clear_smi_status(void); + +/* The initialization of the southbridge is split into 2 compoments. One is + * for clearing the state in the SMM registers. The other is for enabling + * SMIs. They are split so that other work between the 2 actions. */ +void southbridge_smm_clear_state(void); +void southbridge_smm_enable_smi(void); + +#endif diff --git a/src/soc/intel/broadwell/broadwell/systemagent.h b/src/soc/intel/broadwell/broadwell/systemagent.h index 05683a64b5..a0f7a76773 100644 --- a/src/soc/intel/broadwell/broadwell/systemagent.h +++ b/src/soc/intel/broadwell/broadwell/systemagent.h @@ -26,8 +26,6 @@ #define HASWELL_DESKTOP 1 #define HASWELL_SERVER 2 -/* Intel Enhanced Debug region */ -#define IED_SIZE CONFIG_IED_REGION_SIZE #include @@ -183,12 +181,6 @@ #ifndef __ASSEMBLER__ static inline void barrier(void) { asm("" ::: "memory"); } -struct ied_header { - char signature[10]; - u32 size; - u8 reserved[34]; -} __attribute__ ((packed)); - #define PCI_DEVICE_ID_HSW_MOBILE 0x0c04 #define PCI_DEVICE_ID_HSW_ULT 0x0a04 diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index ad71e48eee..12ffa966a6 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -49,22 +49,8 @@ #define SMRR_SUPPORTED (1<<11) #define EMRR_SUPPORTED (1<<12) -struct smm_relocation_params { - u32 smram_base; - u32 smram_size; - u32 ied_base; - u32 ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t emrr_base; - msr_t emrr_mask; - msr_t uncore_emrr_base; - msr_t uncore_emrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE */ - int smm_save_state_in_msrs; -}; +#include +#include /* This gets filled in and used during relocation. */ static struct smm_relocation_params smm_reloc_params; @@ -267,7 +253,7 @@ static void fill_in_relocation_params(device_t dev, params->ied_size = tseg_size - params->smram_size; /* Adjust available SMM handler memory size. */ - params->smram_size -= RESERVED_SMM_SIZE; + params->smram_size -= CONFIG_SMM_RESERVED_SIZE; /* SMRR has 32-bits of valid address aligned to 4KiB. */ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;