From 29faf77d4a2d386bdc0ca92d61e5a23d8935dbad Mon Sep 17 00:00:00 2001 From: Kilian Krause Date: Mon, 27 Oct 2025 10:13:47 +0100 Subject: [PATCH] mb/siemens/mc_rpl1: Limit CPU RP1 to PCIe Gen2 speed Configure CPU root port 1 to operate at PCIe Gen2 speed instead of the default Gen3. This change addresses signal integrity issues on the PCIe link that prevent reliable operation at Gen3 speeds. TEST=Booted on mc_rpl1 and verified CPU RP1 operates at Gen2 speed with `lspci -vv -s 01:00.0 | grep LnkSta`. Output shows `LnkSta: Speed 5GT/s (downgraded), Width x2` Change-Id: I35650d46d4c2ac6942b2e68a4fd23fe875bd0c10 Signed-off-by: Kilian Krause Reviewed-on: https://review.coreboot.org/c/coreboot/+/89765 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer --- src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb index 3c26345eae..ae9f1c0ab4 100644 --- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb +++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb @@ -75,6 +75,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_src = 0, .flags = PCIE_RP_CLK_REQ_UNUSED, + .pcie_rp_pcie_speed = SPEED_GEN2, }" end device ref pcie4_1 on