diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 77008a9345..3be4725763 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -3,7 +3,7 @@
 # TODO: Evaluate what can be moved to a common directory
 # TODO: Update for Glinda
 
-config SOC_AMD_GLINDA
+config SOC_AMD_GLINDA_BASE
 	bool
 	select ACPI_SOC_NVS
 	select ARCH_X86
@@ -96,7 +96,19 @@ config SOC_AMD_GLINDA
 	help
 	  AMD Glinda support
 
-if SOC_AMD_GLINDA
+config SOC_AMD_GLINDA
+	bool
+	select SOC_AMD_GLINDA_BASE
+	help
+	  AMD Glinda support
+
+config SOC_AMD_FAEGAN
+	bool
+	select SOC_AMD_GLINDA_BASE
+	help
+	  AMD Faegan support
+
+if SOC_AMD_GLINDA_BASE
 
 config CHIPSET_DEVICETREE
 	string
@@ -451,4 +463,4 @@ config RWB_REGION_ONLY
 
 endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
 
-endif # SOC_AMD_GLINDA
+endif # SOC_AMD_GLINDA_BASE
diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk
index e0ce02c666..1a71769701 100644
--- a/src/soc/amd/glinda/Makefile.mk
+++ b/src/soc/amd/glinda/Makefile.mk
@@ -3,7 +3,7 @@
 # TODO: Move as much as possible to common
 # TODO: Update for Glinda
 
-ifeq ($(CONFIG_SOC_AMD_GLINDA),y)
+ifeq ($(CONFIG_SOC_AMD_GLINDA_BASE),y)
 
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
 
@@ -315,4 +315,4 @@ build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom
 endif # CONFIG_SEPARATE_SIGNED_PSPFW
 endif
 
-endif # ($(CONFIG_SOC_AMD_GLINDA),y)
+endif # ($(CONFIG_SOC_AMD_GLINDA_BASE),y)
diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c
index 2dcc3c5d21..d414afee4c 100644
--- a/src/soc/amd/glinda/cpu.c
+++ b/src/soc/amd/glinda/cpu.c
@@ -17,6 +17,7 @@ static struct device_operations cpu_dev_ops = {
 static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_AMD, GLINDA_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
 	{ X86_VENDOR_AMD, GLINDA_B0_CPUID, CPUID_ALL_STEPPINGS_MASK },
+	{ X86_VENDOR_AMD, FAEGAN_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
 	CPU_TABLE_END
 };
 
diff --git a/src/soc/amd/glinda/include/soc/cpu.h b/src/soc/amd/glinda/include/soc/cpu.h
index 834b1f94e7..0845cac5cc 100644
--- a/src/soc/amd/glinda/include/soc/cpu.h
+++ b/src/soc/amd/glinda/include/soc/cpu.h
@@ -3,6 +3,8 @@
 #ifndef AMD_GLINDA_CPU_H
 #define AMD_GLINDA_CPU_H
 
-#define GLINDA_A0_CPUID	CPUID_FROM_FMS(0x1a, 0x20, 0)
-#define GLINDA_B0_CPUID	CPUID_FROM_FMS(0x1a, 0x24, 0)
+#define GLINDA_A0_CPUID	CPUID_FROM_FMS(0x1a, 0x20, 0x0)
+#define GLINDA_B0_CPUID	CPUID_FROM_FMS(0x1a, 0x24, 0x0)
+#define FAEGAN_A0_CPUID	CPUID_FROM_FMS(0x1a, 0x68, 0x0)
+
 #endif /* AMD_GLINDA_CPU_H */
diff --git a/src/soc/amd/glinda/include/soc/gpio.h b/src/soc/amd/glinda/include/soc/gpio.h
index 3104889476..7a3a3fcee1 100644
--- a/src/soc/amd/glinda/include/soc/gpio.h
+++ b/src/soc/amd/glinda/include/soc/gpio.h
@@ -115,18 +115,27 @@
 #define GPIO_4_IOMUX_GPIOxx 0
 #define GPIO_5_IOMUX_GPIOxx 0
 #define GPIO_6_IOMUX_GPIOxx 0
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_6_IOMUX_MDIO0_SCL 2
+#endif
 #define GPIO_7_IOMUX_GPIOxx 0
 #define GPIO_7_IOMUX_ZST_STUTTER_RAIL 1
 #define GPIO_8_IOMUX_GPIOxx 0
 #define GPIO_8_IOMUX_TMU_CLK_OUT0 1
 #define GPIO_8_IOMUX_TMU_CLK_OUT1 2
 #define GPIO_9_IOMUX_GPIOxx 0
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_9_IOMUX_MDIO2_SCL 2
+#endif
 #define GPIO_10_IOMUX_GPIOxx 0
 #define GPIO_10_IOMUX_S0A3_GPIO 1
 /* GPIO 10 IOMUX == 2 is also GPIOxx */
 #define GPIO_10_IOMUX_DF_VRCONTEXT_0 3
 #define GPIO_11_IOMUX_GPIOxx 0
 #define GPIO_11_IOMUX_BLINK 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_11_IOMUX_MDIO3_SDA 2
+#endif
 #define GPIO_12_IOMUX_LLB_L 0
 #define GPIO_12_IOMUX_GPIOxx 1
 #define GPIO_16_IOMUX_USB_OC0_L 0
@@ -152,6 +161,9 @@
 #define GPIO_22_IOMUX_SD0_CMD 3
 #define GPIO_23_IOMUX_AC_PRES 0
 #define GPIO_23_IOMUX_GPIOxx 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_23_IOMUX_MDIO2_SDA 2
+#endif
 #define GPIO_24_IOMUX_USB_OC3_L 0
 #define GPIO_24_IOMUX_GPIOxx 1
 #define GPIO_26_IOMUX_PCIE_RST0_L 0
@@ -169,11 +181,23 @@
 #define GPIO_31_IOMUX_SPI2_CS3_L 3
 #define GPIO_32_IOMUX_GPIOxx 0
 #define GPIO_32_IOMUX_LPC_RST_L 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_32_IOMUX_MDIO3_SCL 2
+#endif
 #define GPIO_38_IOMUX_CLK_REQ5_L 0
 #define GPIO_38_IOMUX_GPIOxx 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_38_IOMUX_MDIO1_SDA 2
+#endif
 #define GPIO_39_IOMUX_CLK_REQ6_L 0
 #define GPIO_39_IOMUX_GPIOxx 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_39_IOMUX_MDIO1_SCL 2
+#endif
 #define GPIO_40_IOMUX_GPIOxx 0
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_40_IOMUX_MDIO0_SDA 2
+#endif
 #define GPIO_42_IOMUX_GPIOxx 0
 #define GPIO_42_IOMUX_DF_VRCONTEXT_1 1
 #define GPIO_67_IOMUX_SPI_ROM_REQ 0
@@ -257,13 +281,22 @@
 #define GPIO_135_IOMUX_UART3_TXD 2
 #define GPIO_136_IOMUX_GPIOxx 0
 #define GPIO_136_IOMUX_UART2_RXD 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_136_IOMUX_XGBE_LED0 2
+#endif
 #define GPIO_137_IOMUX_GPIOxx 0
 #define GPIO_137_IOMUX_UART2_RTS_L 1
 #define GPIO_137_IOMUX_UART3_RXD 2
 #define GPIO_138_IOMUX_GPIOxx 0
 #define GPIO_138_IOMUX_UART2_TXD 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_138_IOMUX_XGBE_LED1 2
+#endif
 #define GPIO_139_IOMUX_GPIOxx 0
 #define GPIO_139_IOMUX_UART2_INTR 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_139_IOMUX_XGBE_LED2 2
+#endif
 #define GPIO_140_IOMUX_GPIOxx 0
 #define GPIO_140_IOMUX_UART0_CTS_L 1
 #define GPIO_140_IOMUX_UART1_TXD 2
@@ -291,13 +324,28 @@
 #define GPIO_148_IOMUX_GPIOxx 2
 #define GPIO_153_IOMUX_GPIOxx 0
 #define GPIO_153_IOMUX_UART4_CTS_L 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_153_IOMUX_XGBE_LED3 2
+#endif
 #define GPIO_154_IOMUX_GPIOxx 0
 #define GPIO_154_IOMUX_UART4_RTS_L 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_154_IOMUX_XGBE_LED4 2
+#endif
 #define GPIO_155_IOMUX_GPIOxx 0
 #define GPIO_155_IOMUX_UART4_RXD 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_155_IOMUX_XGBE_LED5 2
+#endif
 #define GPIO_156_IOMUX_GPIOxx 0
 #define GPIO_156_IOMUX_UART4_TXD 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_156_IOMUX_XGBE_LED6 2
+#endif
 #define GPIO_157_IOMUX_GPIOxx 0
 #define GPIO_157_IOMUX_UART4_INTR 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_157_IOMUX_XGBE_LED7 2
+#endif
 
 #endif /* AMD_GLINDA_GPIO_H */