From 23e92a5ac0f94e6914b1eafa5c86d9e5091f990d Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Fri, 8 Aug 2025 02:30:50 +0200
Subject: [PATCH] mb/erying/tgl: Map remaining USB ports

All USB ports are working \o/

Change-Id: I49aa8a245f656b8b6e47ce3a0e69899c052cf3f3
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88716
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 src/mainboard/erying/tgl/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/erying/tgl/devicetree.cb b/src/mainboard/erying/tgl/devicetree.cb
index c6cd68d1ae..2558bd6c62 100644
--- a/src/mainboard/erying/tgl/devicetree.cb
+++ b/src/mainboard/erying/tgl/devicetree.cb
@@ -74,10 +74,13 @@ chip soc/intel/tigerlake
 				[3] = USB2_PORT_MID(OC_SKIP),		/* NIC right */
 				[4] = USB2_PORT_MID(OC_SKIP),		/* Front Panel 1 */
 				[5] = USB2_PORT_MID(OC_SKIP),		/* Front Panel 2 */
+				[6] = USB2_PORT_MID(OC_SKIP),		/* Front Panel 3 */
+				[7] = USB2_PORT_MID(OC_SKIP),		/* Front Panel 4 */
 				[8] = USB2_PORT_MID(OC_SKIP),		/* Front Panel 1 (USB3) */
 				[9] = USB2_PORT_MID(OC_SKIP),		/* Front Panel 2 (USB3) */
 				[10] = USB2_PORT_MID(OC_SKIP),		/* Rear, top left */
 				[11] = USB2_PORT_MID(OC_SKIP),		/* Rear, top right */
+				[12] = USB2_PORT_MID(OC_SKIP),		/* M.2 NGFF (Bluetooth) */
 			}"
 
 			register "usb3_ports" = "{