diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 47c81e6e74..6a2d3bfbab 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -6,6 +6,7 @@ config BOARD_GOOGLE_BLUEY_COMMON
 	# FIXME: keep ADB for development phase
 	select GBB_FLAG_ENABLE_ADB if VBOOT
 	select MAINBOARD_HAS_CHROMEOS
+	select SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT
 	select SPI_FLASH
 	select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE
 	select SPI_FLASH_INCLUDE_ALL_DRIVERS
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 891809f045..042e69b9f0 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -10,6 +10,7 @@
 #include <gpio.h>
 #include <security/vboot/vboot_common.h>
 #include <soc/aop_common.h>
+#include <soc/pcie.h>
 #include <soc/pmic.h>
 #include <soc/qclib_common.h>
 #include <soc/shrm.h>
@@ -188,4 +189,8 @@ void platform_romstage_postram(void)
 		*boot_mode_ptr = boot_mode;
 		printk(BIOS_INFO, "Boot mode is %d\n", *boot_mode_ptr);
 	}
+
+	/* Perform PCIe setup early in async mode if supported to save 100ms */
+	if (boot_mode == LB_BOOT_MODE_NORMAL)
+		qcom_setup_pcie_host(NULL);
 }