samus: Delay bringing SSD out of reset

In order to ensure that we meet timing requirements for the SSD
power sequencing delay bringing the SSD out of reset until after
memory training.

BUG=chrome-os-partner:29914
BRANCH=None
TEST=build and boot on samus

Change-Id: I807e3d3698255287c3fe7219f44e8ec9a0985df1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/208155
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-07-15 13:41:18 -07:00 committed by chrome-internal-fetch
commit 1cf557049c
2 changed files with 5 additions and 1 deletions

View file

@ -23,6 +23,7 @@
#include <broadwell/gpio.h>
#define SAMUS_GPIO_PP3300_AUTOBAHN_EN 23
#define SAMUS_GPIO_SSD_RESET_L 47
static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
@ -72,7 +73,7 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 44: UNUSED */
PCH_GPIO_PIRQ, /* 45: DSP_INT (PIRQN) */
PCH_GPIO_PIRQ, /* 46: HOTWORD_DET_L (PIRQO) */
PCH_GPIO_OUT_HIGH, /* 47: SSD_RESET_L */
PCH_GPIO_OUT_LOW, /* 47: SSD_RESET_L */
PCH_GPIO_UNUSED, /* 48: UNUSED */
PCH_GPIO_UNUSED, /* 49: UNUSED */
PCH_GPIO_UNUSED, /* 50: UNUSED */

View file

@ -67,6 +67,9 @@ void mainboard_romstage_entry(struct romstage_params *rp)
/* Initliaze memory */
romstage_common(rp);
/* Bring SSD out of reset */
set_gpio(SAMUS_GPIO_SSD_RESET_L, GPIO_OUT_HIGH);
/*
* Enable PP3300_AUTOBAHN_EN after initial GPIO setup
* to prevent possible brownout.