diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk
index 5e8c91fbb5..655e14df03 100644
--- a/payloads/external/Makefile.mk
+++ b/payloads/external/Makefile.mk
@@ -199,6 +199,7 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
 		CONFIG_EDK2_UFS_ENABLE=$(CONFIG_EDK2_UFS_ENABLE) \
 		CONFIG_EDK2_PCO_MMIO_EMMC=$(CONFIG_EDK2_PCO_MMIO_EMMC) \
 		CONFIG_EDK2_USE_LAPIC_TIMER=$(CONFIG_EDK2_USE_LAPIC_TIMER) \
+		CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2=$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \
diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index 0908f4d26c..358c8c6125 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -115,6 +115,12 @@ endif
 ifeq ($(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS), y)
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport=TRUE
 endif
+# Preserve VRT bit in RTC_ADDRESS_REGISTER_D
+# AMD SoC sets this every 1.024msec, but the generic code assumes it's read-only and
+# hardcoded to 1 like on every Intel chipset since Intel ICH.
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2), y)
+BUILD_STR += --pcd gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD=0x80
+endif
 
 #
 # The MrChromebox repository has the following addition options: