From 1044f03878c30a12ebc6ce20641b4358204d2327 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 22 Apr 2025 10:48:00 +0200 Subject: [PATCH] payloads/external/edk2: Set StatusD register to work around failing AMD boot On recent AMD platforms the VRT bit in the StatusD register is read-writeable and set every 1024msec when RTC power is good. This leads to a timeout in RtcWaitToUpdate() waiting for the bit to be set and the gEfiRealTimeClockArchProtocolGuid won't be installed. The protocol is critical to boot. Adjust the code to not clear the VRT bit, as RtcWaitToUpdate() will return an error, as it assumes the VRT bit is read-only and hardwired to one as on Intel ICHs. While the timeout could be increased it would also increase boot time by up to a second. On platforms where the VRT bit is read-only the introduced code does the same as before. Change-Id: I8bc432114c83fa5f5fb35a144e3a35c38ee8a3de Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/87415 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel --- payloads/external/Makefile.mk | 1 + payloads/external/edk2/Makefile | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index 5e8c91fbb5..655e14df03 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -199,6 +199,7 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) CONFIG_EDK2_UFS_ENABLE=$(CONFIG_EDK2_UFS_ENABLE) \ CONFIG_EDK2_PCO_MMIO_EMMC=$(CONFIG_EDK2_PCO_MMIO_EMMC) \ CONFIG_EDK2_USE_LAPIC_TIMER=$(CONFIG_EDK2_USE_LAPIC_TIMER) \ + CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2=$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 0908f4d26c..358c8c6125 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -115,6 +115,12 @@ endif ifeq ($(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS), y) BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport=TRUE endif +# Preserve VRT bit in RTC_ADDRESS_REGISTER_D +# AMD SoC sets this every 1.024msec, but the generic code assumes it's read-only and +# hardcoded to 1 like on every Intel chipset since Intel ICH. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2), y) +BUILD_STR += --pcd gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD=0x80 +endif # # The MrChromebox repository has the following addition options: