From 0d1545ffacff4ba2016557766c9b2eb2fc7b6496 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Wed, 24 Sep 2025 14:11:57 -0700 Subject: [PATCH] soc/intel/pantherlake: Add hysteresis window UPDs support This commit introduces configuration options for P-core and E-core hysteresis time windows to support acoustic noise mitigation on Intel Panther Lake (PTL) System on Chips (SoCs). Change-Id: Ic3bceda06adf4e0a81b0503e5fb65895bfad2c12 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/89333 Reviewed-by: Jamie Ryu Tested-by: build bot (Jenkins) Reviewed-by: Cliff Huang --- src/soc/intel/pantherlake/chip.h | 4 ++++ src/soc/intel/pantherlake/romstage/fsp_params.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index cb37155adb..d9da2d1b26 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -651,6 +651,10 @@ struct soc_intel_pantherlake_config { * as per `enum slew_rate` data type. */ uint8_t slow_slew_rate_config[NUM_VR_DOMAINS]; + /* P-cores Hysteresis time window ranges from 1 to 50 ms. */ + uint8_t pcore_hysteresis_window_ms; + /* E-cores Hysteresis time window ranges from 1 to 50 ms. */ + uint8_t ecore_hysteresis_window_ms; uint16_t max_dram_speed_mts; diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 30b4eac48a..2a30bd3599 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -363,6 +363,8 @@ static void fill_fspm_acoustic_params(FSP_M_CONFIG *m_cfg, return; m_cfg->AcousticNoiseMitigation = config->enable_acoustic_noise_mitigation; + m_cfg->PcoreHysteresisWindow = config->pcore_hysteresis_window_ms; + m_cfg->EcoreHysteresisWindow = config->ecore_hysteresis_window_ms; for (size_t i = 0; i < ARRAY_SIZE(config->disable_fast_pkgc_ramp); i++) { m_cfg->FastPkgCRampDisable[i] = config->disable_fast_pkgc_ramp[i];