From 0b03ecbc44610398576c39ee8b86ea4647b7782b Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 12 Mar 2025 08:31:56 +0100 Subject: [PATCH] soc/amd/glinda: Fix PSP_SOFTFUSE_BITS The PSP_SOFTFUSE_BITs were probably copy&pasted during initial SoC bringup and need to be adjusted: * Drop PSP_SOFTFUSE_BIT BIT28 as it causes PSP to hang. * Drop PSP_SOFTFUSE_BIT BIT34 as it's not required. This also moves coreboot closer to the UEFI reference firmware. Document #55758 Rev. 2.04 TEST: Booted on amd/birman_plus with default PSP_SOFTFUSE_BITS. Change-Id: Ic7b2b0ac01fe0ac0ed2535254f242a8068f9b02a Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/86840 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Ana Carolina Cabral Reviewed-by: Felix Held Reviewed-by: Andy Ebrahiem --- src/soc/amd/glinda/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 1bd5b2f179..a0d64c62d7 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -356,7 +356,7 @@ config PSP_WHITELIST_FILE config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" - default "34 28 6" + default "6" help Space separated list of Soft Fuse bits to enable. Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)