From 0af68855c09d454a41e7769e1a31c651c9ff6278 Mon Sep 17 00:00:00 2001 From: Jianeng Ceng Date: Fri, 30 May 2025 12:59:26 +0800 Subject: [PATCH] mb/google/nissa/var/pujjoniru: Config AUX gpio to correct TCSS port In TWL, Type-C0 corresponds to TCSS port1, and Type-C1 corresponds to TCSS port0. In order for the DP functions of the two Type-C ports to operate normally, the corresponding relationship needs to be configured correctly. BUG=b:418106736 TEST=DP function of Type-C0/C1 workable Change-Id: I4aa406e72d1e5f0434866b105f20df6362f3d304 Signed-off-by: Jianeng Ceng Reviewed-on: https://review.coreboot.org/c/coreboot/+/87899 Reviewed-by: Kapil Porwal Reviewed-by: hualin wei Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/mainboard/google/brya/variants/pujjoniru/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb index 60d3117d05..cc3d1dcefc 100644 --- a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb @@ -27,12 +27,12 @@ chip soc/intel/alderlake # motherboard to USBC connector register "tcss_aux_ori" = "5" - register "typec_aux_bias_pads[0]" = "{ + register "typec_aux_bias_pads[1]" = "{ .pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23 }" - register "typec_aux_bias_pads[1]" = "{ + register "typec_aux_bias_pads[0]" = "{ .pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22 }"