From 0660fe50de161591259ba9c1ffffe7da8e7c20f8 Mon Sep 17 00:00:00 2001 From: "P, Usha" Date: Mon, 16 Jun 2025 11:58:30 +0530 Subject: [PATCH] mb/google/ocelot: Update GPE configuration This patch updates the GPE configuration for Ocelot in baseboard devicetree based on schematic_1433518. BUG=b:394208231, b:430001789 TEST=Build Ocelot and verify it compiles without any error. Change-Id: I60bcf586ab8653732925bfd9393baef226519c3a Signed-off-by: P, Usha Reviewed-on: https://review.coreboot.org/c/coreboot/+/88106 Reviewed-by: Krishna P Bhat D Reviewed-by: Nick Vaccaro Reviewed-by: Sowmya Aralguppe Tested-by: build bot (Jenkins) --- .../google/ocelot/variants/baseboard/ocelot/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb index b79a3b3674..3c8ab4f7b1 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb +++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/pantherlake # GPE configuration - register "pmc_gpe0_dw0" = "GPP_A" - register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw0" = "GPP_VGPIO" + register "pmc_gpe0_dw1" = "GPP_B" register "pmc_gpe0_dw2" = "GPP_E" # For Ocelot variants with microchip EC: