diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index b79a3b3674..3c8ab4f7b1 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -1,7 +1,7 @@
 chip soc/intel/pantherlake
 	# GPE configuration
-	register "pmc_gpe0_dw0" = "GPP_A"
-	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw0" = "GPP_VGPIO"
+	register "pmc_gpe0_dw1" = "GPP_B"
 	register "pmc_gpe0_dw2" = "GPP_E"
 
 	# For Ocelot variants with microchip EC: