From 05ec649338f73b1a5f8588028ea60515d2083e2d Mon Sep 17 00:00:00 2001 From: John Su Date: Fri, 28 Mar 2025 10:21:49 +0800 Subject: [PATCH] mb/var/uldrenite: Configure descriptor for either MBVR or FIVR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since we need to support both MBVR (MotherBoard Voltage Regulator) and FIVR (Fully Integrated Voltage Regulator) in this phase, the FIT setting is initially set to FIVR. This causes MBVR boards to have two voltage sources, potentially triggering OVP and leading to reboots during the boot process. The current build's main source is MBVR, so we want to use fw_config to dynamically adjust MFIT and MBVR with the current phase devices to ensure consistency in client devices settings. Refer to Intel#822618 and set PMC Descriptor Record 7, bit 30 (VCCANA VR Location) accordingly. And then CONFIGURE_DESCRIPTOR is a temporary workaround for the current phase. In the next phase, we will choose a specific setting for implementation. If there are any concerns, we use the board ID to restrict it. BUG=b:404126972 TEST=boot to ChromeOS Change-Id: I337574c8c55889ceb49b9f33625feadb48bd8890 Signed-off-by: John Su Reviewed-on: https://review.coreboot.org/c/coreboot/+/87033 Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Dinesh Gehlot --- src/mainboard/google/brya/Kconfig | 1 + .../brya/variants/uldrenite/Makefile.mk | 1 + .../google/brya/variants/uldrenite/variant.c | 29 +++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 88869018a4..5331f0e42f 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -669,6 +669,7 @@ config BOARD_GOOGLE_ULDREN select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_ULDRENITE + select ALDERLAKE_CONFIGURE_DESCRIPTOR select BOARD_GOOGLE_BASEBOARD_TRULO select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_WWAN_FM350GL diff --git a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk index c31fa307d0..0f152afe62 100644 --- a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk +++ b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +bootblock-y += variant.c romstage-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c index 421799694a..cbaf20bac8 100644 --- a/src/mainboard/google/brya/variants/uldrenite/variant.c +++ b/src/mainboard/google/brya/variants/uldrenite/variant.c @@ -2,10 +2,12 @@ #include #include +#include #include #include #include #include +#include const char *get_wifi_sar_cbfs_filename(void) { @@ -75,3 +77,30 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) printk(BIOS_INFO, "Configured External FIVR\n"); } } + +void variant_update_descriptor(void) +{ + uint32_t board_version = board_id(); + + /* b/404126972: Only this phase has M/B with both FIVR and MBVR. */ + if (board_version != 1) + return; + + /* VccanaVrLocation = "VCCANA is CPU FIVR" */ + struct descriptor_byte fivr_bytes[] = { + { 0xc33, 0x32 } + }; + + /* VccanaVrLocation = "VCCANA is Platform VR" */ + struct descriptor_byte mbvr_bytes[] = { + { 0xc33, 0x72 } + }; + + if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_PRESENT))) { + printk(BIOS_INFO, "Configuring descriptor for MBVR\n"); + configure_descriptor(mbvr_bytes, ARRAY_SIZE(mbvr_bytes)); + } else { + printk(BIOS_INFO, "Configuring descriptor for FIVR\n"); + configure_descriptor(fivr_bytes, ARRAY_SIZE(fivr_bytes)); + } +}