From 051516af1add5c1c54cc0fde03c5b0345e12132d Mon Sep 17 00:00:00 2001 From: Appukuttan V K Date: Mon, 19 Jan 2026 23:31:54 +0530 Subject: [PATCH] soc/intel/pantherlake: Consolidate WCL SKUs and update GT VR settings Simplify Wildcat Lake SKU configuration by consolidating multiple SKU variants into a single WCL_SKU_1 configuration. All WCL device IDs (WCL_ID_2 through WCL_ID_5) now map to WCL_SKU_1 instead of having separate SKU definitions. Additionally, update GT domain VR controller settings for WCL_SKU_1: - Set IccMax to 36A (144 in register units) for GT domain BUG=b:467349691 TEST=Build ocelot and verify system boots with consolidated WCL SKU configuration. Confirm GT VR IccMax is set to 36A in coreboot logs. Change-Id: I6466c150bcd712430cf2595db5be13039688fecb Signed-off-by: Appukuttan V K Reviewed-on: https://review.coreboot.org/c/coreboot/+/90803 Reviewed-by: Matt DeVillier Reviewed-by: P, Usha Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/chip.h | 12 ++++-------- src/soc/intel/pantherlake/chipset_wcl.cb | 4 ++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 1301813aaf..15a1501e18 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -78,10 +78,6 @@ enum soc_intel_pantherlake_sku { PTL_SKU_6, PTL_SKU_7, WCL_SKU_1, - WCL_SKU_2, - WCL_SKU_3, - WCL_SKU_4, - WCL_SKU_5, MAX_PTL_SKUS, }; @@ -119,10 +115,10 @@ static const struct soc_intel_pantherlake_power_map { { PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_7, PTL_TDC_4 }, { PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2, PTL_TDC_3 }, { PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 }, - { PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2, WCL_TDC_1 }, - { PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3, WCL_TDC_1 }, - { PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_4, WCL_TDC_1 }, - { PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_5, WCL_TDC_1 }, + { PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 }, + { PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 }, + { PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 }, + { PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 }, }; /* Types of display ports */ diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb index 465ad05ad9..4d8d296aa5 100644 --- a/src/soc/intel/pantherlake/chipset_wcl.cb +++ b/src/soc/intel/pantherlake/chipset_wcl.cb @@ -8,6 +8,10 @@ chip soc/intel/pantherlake .tdp_pl4 = 93, }" + register "icc_max[WCL_SKU_1]" = "{ + [VR_DOMAIN_GT] = 36 * 4, + }" + # Reduce the size of BasicMemoryTests to speed up the boot time. register "lower_basic_mem_test_size" = "true"