diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 1301813aaf..15a1501e18 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -78,10 +78,6 @@ enum soc_intel_pantherlake_sku {
 	PTL_SKU_6,
 	PTL_SKU_7,
 	WCL_SKU_1,
-	WCL_SKU_2,
-	WCL_SKU_3,
-	WCL_SKU_4,
-	WCL_SKU_5,
 	MAX_PTL_SKUS,
 };
 
@@ -119,10 +115,10 @@ static const struct soc_intel_pantherlake_power_map {
 	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_7, PTL_TDC_4 },
 	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2, PTL_TDC_3 },
 	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
-	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2, WCL_TDC_1 },
-	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3, WCL_TDC_1 },
-	{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_4, WCL_TDC_1 },
-	{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_5, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
 };
 
 /* Types of display ports */
diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index 465ad05ad9..4d8d296aa5 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -8,6 +8,10 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 93,
 	}"
 
+	register "icc_max[WCL_SKU_1]" = "{
+		[VR_DOMAIN_GT] = 36 * 4,
+	}"
+
 	# Reduce the size of BasicMemoryTests to speed up the boot time.
 	register "lower_basic_mem_test_size" = "true"