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exynos5420: enable DMC internal clock gating

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lets enable memory controller internal clock gating for ddr3.
with these bits enabled we save some power out of ddr3.

This is ported from https://gerrit.chromium.org/gerrit/#/c/60774

Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
BRANCH=none
TEST=built and booted on pit

Change-Id: I2f9b0d78483b3ea7441f54a715c7c1e42eda3f7f
Reviewed-on: https://gerrit.chromium.org/gerrit/65728
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
David Hendricks 2013-08-09 16:07:07 -07:00 • committed by ChromeBot
commit 022a81c44e
2 changed files with 16 additions and 0 deletions
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8
src/cpu/samsung/exynos5420/dmc_init_ddr3.c
View file

@ -376,5 +376,13 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
&drex1->concontrol);
/* Enable Clock Gating Control for DMC
* this saves around 25 mw dmc power as compared to the power
* consumption without these bits enabled
*/
setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
return 0;
}

8
src/cpu/samsung/exynos5420/setup.h
View file

@ -791,6 +791,14 @@ struct exynos5_phy_control;
#define BRBRSVCONTROL_VAL 0x00000033
#define BRBRSVCONFIG_VAL 0x88778877
/* Clock Gating Control (CGCONTROL) register */
#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */
#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */
#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */
#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \
BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
/* DMC PHY Control0 register */
#define PHY_CONTROL0_RESET_VAL 0x0
#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */